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PRELIMINARY
KM6161002A, KM6161002AI
Document Title
64Kx16 Bit High Speed Static RAM(5V Operating), Revolutionary Pin out. Operated at Commercial and Industrial Temperature Range.
CMOS SRAM
Revision History
Rev. No. Rev. 0.0 Rev. 1.0 History Initial release with Preliminary. Release to final Data Sheet. 1.1. Delete Preliminary Update D.C parameters. 2.1. Update D.C parameters.
Items Icc Isb Isb1 Previous spec. (12/15/17/20ns part) 220/210/200/190mA 30mA 10mA Updated spec. (12/15/17/20ns part) 190/185/185/180mA 25mA 8mA
Draft Data Apr. 22th, 1995 Feb. 29th, 1996
Remark Preliminary Final
Rev. 2.0
Jul. 16th, 1996
Final
Rev. 3.0
Add Industrial Temperature Range parts 3.1. Add Industrial Temperature Range parts with the same parameters as Commercial Temperature Range parts. 3.1.1. Add KM6161002AI parts for Industrial Temperature Range. 3.1.2. Add ordering information. 3.1.3. Add the condition for operating at Industrial Temp. Range. 3.2. Add the test condition for Voh1 with Vcc=5V5% at 25C 3.3. Add timing diagram to define tWP1 as (Timing Wave Form of Write Cycle(OE=Low fixed) 4.1. Delete 17ns Part
Jun. 2nd, 1997
Final
Rev. 4.0
Feb. 25th, 1998
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
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Rev 4.0 February 1998
PRELIMINARY
KM6161002A, KM6161002AI
64K x 16 Bit High-Speed CMOS Static RAM
FEATURES
* Fast Access Time 12, 15, 20ns(Max.) * Low Power Dissipation Standby (TTL) : 25mA(Max.) (CMOS) : 8mA(Max.) Operating KM6161002A - 12 : 190mA(Max.) KM6161002A - 15 : 185mA(Max.) KM6161002A - 20 : 180mA(Max.) * Single 5.0V 10% Power Supply * TTL Compatible Inputs and Outputs * I/O Compatible with 3.3V Device * Fully Static Operation - No Clock or Refresh required * Three State Outputs * Center Power/Ground Pin Configuration * Data Byte Control : LB:I/O1~I/O8, UB:I/O9~I/O16 * Standard Pin Configuration KM6161002AJ : 44-SOJ-400 KM6161002AT : 44-TSOP2-400F
CMOS SRAM
GENERAL DESCRIPTION
The KM6161002A is a 1,048,576-bit high-speed Static Random Access Memory organized as 65,536 words by 16 bits. The KM6161002A uses 16 common input and output lines and has an output enable pin which operates faster than address access time at read cycle. Also it allows that lower and upper byte access by data byte control(UB, LB). The device is fabricated using SAMSUNGs advanced CMOS process and designed for high-speed circuit technology. It is particularly well suited for use in high-density high-speed system applications. The KM6161002A is packaged in a 400mil 44-pin plastic SOJ or TSOP2 forward.
PIN CONFIGURATION (Top View)
A0 A1 A2 A3 A4 1 2 3 4 5 6 7 8 9 44 A15 43 A14 42 A13 41 OE 40 UB 39 LB 38 I/O16 37 I/O15 36 I/O14
ORDERING INFORMATION
KM6161002A -12/15/20 KM6161002AI -12/15/20 Commercial Temp. Industrial Temp.
CS I/O1 I/O2 I/O3
I/O4 10 Vcc 11
SOJ/ TSOP2
35 I/O13 34 Vss 33 Vcc 32 I/O12 31 I/O11 30 I/O10 29 I/O9 28 N.C. 27 A12 26 A11 25 A10 24 A9 23 N.C.
FUNCTIONAL BLOCK DIAGRAM
Clk Gen.
A1 A2 A3 A4 A5 A6 A7 A8 A9 I/O1~I/O8 I/O9~I/O16
Vss 12 I/O5 13 I/O6 14 I/O7 15 I/O8 16 WE 17 A5 18
Pre-Charge Circuit
Row Select
A6 19
Memory Array 512 Rows 128x16 Columns
A7 20 A8 21 N.C. 22
Data Cont. Data Cont. Gen. CLK
I/O Circuit & Column Select
PIN FUNCTION
Pin Name A0 - A15 WE Pin Function Address Inputs Write Enable Chip Select Output Enable Lower-byte Control(I/O1~I/O8) Upper-byte Control(I/O9~I/O16) Data Inputs/Outputs Power(+5.0V) Ground No Connection
A0 A10 A11 A12 A13 A14 A15
CS OE LB
WE OE UB LB CS
UB I/O1 ~ I/O16 VCC VSS N.C
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Rev 4.0 February 1998
PRELIMINARY
KM6161002A, KM6161002AI
ABSOLUTE MAXIMUM RATINGS*
Parameter Voltage on Any Pin Relative to VSS Voltage on VCC Supply Relative to VSS Power Dissipation Storage Temperature Operating Temperature Commercial Industrial Symbol VIN, VOUT VCC PD TSTG TA TA Rating -0.5 to 7.0 -0.5 to 7.0 1.0 -65 to 150 0 to 70 -40 to 85 Unit V V W C C C
CMOS SRAM
* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS(TA=0 to 70C)
Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min 4.5 0 2.2 -0.5* Typ 5.0 0 Max 5.5 0 VCC + 0.5** 0.8 Unit V V V V
NOTE: The above parameters are also guaranteed at industrial temperature range. * VIL(Min) = -2.0V a.c(Pulse Width10ns) for I20mA ** VIH(Max) = VCC + 2.0V a.c (Pulse Width10ns) for I20mA
DC AND OPERATING CHARACTERISTICS(TA=0 to 70C, Vcc=5.0V10%, unless otherwise specified)
Parameter Input Leakage Current Output Leakage Current Operating Current Symbol ILI ILO ICC Test Conditions VIN = VSS to VCC CS=VIH or OE=VIH or WE=VIL VOUT = VSS to VCC Min. Cycle, 100% Duty CS=VIL, VIN = VIH or VIL, IOUT=0mA Min. Cycle, CS=VIH f=0MHz, CS VCC-0.2V, VINVCC-0.2V or VIN0.2V IOL=8mA IOH=-4mA IOH1=-0.1mA 12ns 15ns 20ns Standby Current ISB ISB1 Output Low Voltage Level Output High Voltage Level VOL VOH VOH1* Min -2 -2 2.4 Max 2 2 190 185 180 25 8 0.4 3.95 mA mA V V V Unit A A mA
NOTE: The above parameters are also guaranteed at industrial temperature range. * VCC=5.0V, Temp=25C
CAPACITANCE*(TA=25C, f=1.0MHz)
Item Input/Output Capacitance Input Capacitance Symbol CI/O CIN Test Conditions VI/O=0V VIN=0V MIN Max 8 6 Unit pF pF
* NOTE : Capacitance is sampled and not 100% tested.
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Rev 4.0 February 1998
PRELIMINARY
KM6161002A, KM6161002AI
AC CHARACTERISTICS(TA=0 to 70C, VCC=5.0V10%, unless otherwise noted.)
TEST CONDITIONS
Parameter Input Pulse Levels Input Rise and Fall Times Input and Output timing Reference Levels Output Loads
NOTE: The above test conditions are also applied at industrial temperature range.
CMOS SRAM
Value 0V to 3V 3ns 1.5V See below
Output Loads(A) +5.0V 480 DOUT 255 30pF*
Output Loads(B) for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ +5.0V 480 DOUT 255 5pF*
* Including Scope and Jig Capacitance
READ CYCLE
Parameter Read Cycle Time Address Access Time Chip Select to Output Output Enable to Valid Output UB, LB Access Time Chip Enable to Low-Z Output Output Enable to Low-Z Output UB, LB Enable to Low-Z Output Chip Disable to High-Z Output Output Disable to High-Z Output UB, LB Disable to High-Z Output Output Hold from Address Change Symbol tRC tAA tCO tOE tBA tLZ tOLZ tBLZ tHZ tOHZ tBHZ tOH KM6161002A-12 Min 12 3 0 0 0 0 0 3 Max 12 12 6 6 6 6 6 KM6161002A-15 Min 15 3 0 0 0 0 0 3 Max 15 15 7 7 7 7 7 KM6161002A-20 Min 20 3 0 0 0 0 0 3 Max 20 20 9 9 9 9 9 Unit ns ns ns ns ns ns ns ns ns ns ns ns
NOTE: The above parameters are also guaranteed at industrial temperature range.
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Rev 4.0 February 1998
PRELIMINARY
KM6161002A, KM6161002AI
WRITE CYCLE
Parameter Write Cycle Time Chip Select to End of Write Address Set-up Time Address Valid to End of Write Write Pulse Width(OE High) Write Pulse Width(OE Low) UB, LB Valid to End of Write Write Recovery Time Write to Output High-Z Data to Write Time Overlap Data Hold from Write Time End Write to Output Low-Z Symbol tWC tCW tAS tAW tWP tWP1 tBW tWR tWHZ tDW tDH tOW KM6161002A-12 Min 12 8 0 8 8 12 8 0 0 6 0 3 Max 6 KM6161002A-15 Min 15 10 0 10 10 15 10 0 0 7 0 3 Max 7 KM6161002A-20 Min 20 12 0 12 12 20 12 0 0 9 0 3 Max 9 Unit ns ns ns ns ns ns ns ns ns ns ns ns
CMOS SRAM
NOTE: The above parameters are also guaranteed at industrial temperature range.
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH, UB, LB=VIL)
tRC Address tOH Data Out Previous Valid Data tAA Valid Data
-5-
Rev 4.0 February 1998
PRELIMINARY
KM6161002A, KM6161002AI
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC Address tAA tCO tBA UB, LB tBLZ(4,5) OE tOLZ Data out
High-Z
CMOS SRAM
tHZ(3,4,5)
CS
tBHZ(3,4,5)
tOHZ tOE tOH Valid Data
tLZ(4,5)
NOTES(READCYCLE) 1. WE is high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address. 3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or VOL levels. 4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device. 5. Transition is measured 200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested. 6. Device is continuously selected with CS=VIL. 7. Address valid prior to coincident with CS transition low. 8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
TIMING WAVEFORM OF WRITE CYCLE(1) (OE Clock)
tWC Address tAW OE tCW(3) CS tBW UB, LB tAS(4) WE tDW Data in High-Z tOHZ(6) Data out Valid Data tDH High-Z tWP(2) tWR(5)
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Rev 4.0 February 1998
PRELIMINARY
KM6161002A, KM6161002AI
TIMING WAVEFORM OF WRITE CYCLE(2) (OE =Low fixed)
tWC Address tAW tCW(3) CS tBW UB, LB tAS(4) WE tDW Data in High-Z tWHZ(6) Data out High-Z Valid Data tOW
(10) (9)
CMOS SRAM
tWR(5)
tWP1(2)
tDH
TIMING WAVEFORM OF WRITE CYCLE(3) (CS=Controlled)
tWC Address tAW tCW(3) CS tBW UB, LB tAS(4) WE tDW Data in tDH tWP(2) tWR(5)
High-Z
tLZ tWHZ(6)
Valid Data
High-Z
Data out
High-Z
High-Z(8)
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Rev 4.0 February 1998
PRELIMINARY
KM6161002A, KM6161002AI
TIMING WAVEFORM OF WRITE CYCLE(4) (UB, LB Controlled)
tWC Address tAW tCW(3) CS tBW UB, LB tAS(4) WE tDW Data in tDH tWP(2) tWR(5)
CMOS SRAM
High-Z
Valid Data tBLZ tWHZ(6)
Data out
High-Z
High-Z(8)
NOTES(WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low CS,WE,LB and UB. A write begins at the latest transition CS going low and WE going low ; A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of CS going low to end of write. 4. AS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high. 6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state. 9. Dout is the read data of the new address. 10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied.
FUNCTIONAL DESCRIPTION
CS H L L L WE X H X H OE X* H X L LB X X H L H L L L X L H L
* NOTE : X means Dont Care.
UB X X H H L L H L L
Mode I/O1~I/O8 Not Select Output Disable High-Z High-Z
I/O Pin I/O9~I/O16 High-Z High-Z
Supply Current ISB, ISB1 ICC
Read
DOUT High-Z DOUT
High-Z DOUT DOUT High-Z DIN DIN
ICC
Write
DIN High-Z DIN
ICC
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Rev 4.0 February 1998
PRELIMINARY
KM6161002A, KM6161002AI
PACKAGE DIMENSIONS
44-SOJ-400
Units:millimeters/Inches
CMOS SRAM
#44
#23
11.18 0.12 0.440 0.005
10.16 0.400
9.40 0.25 0.370 0.010
0.20 +0.10 -0.05 0.008 +0.004 -0.002 #1 28.98 MAX 1.141 25.58 0.12 1.125 0.005 ( 1.19 ) 0.047 3.76 1.27 ( 0.050 ) 0.148 MAX 0.10 MAX 0.004 #22 0.69 MIN 0.027
( 0.95 ) 0.0375
0.43 -0.05 0.017 +0.004 -0.002
+0.10
1.27 0.050
0.71 -0.05 0.028 +0.004 -0.002
+0.10
44-TSOP2-400F
Units:millimeters/Inches
0~8 0.25 ( ) 0.010
#44
#23
0.45 ~0.75 0.018 ~ 0.030
11.76 0.20 0.463 0.008
10.16 0.400
#1 18.81 MAX. 0.741 18.41 0.10 0.725 0.004
#22
0 + 0.1 0.05 0.15 - .00 4 +0 02 .006 - 0.0
( 0.50 ) 0.020
0
1.00 0.10 0.039 0.004 ( 0.805 ) 0.032 0.35 0.10 0.014 0.004 0.80 0.0315 0.05 MIN. 0.002
1.20 MAX. 0.047
0.10 MAX 0.004
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Rev 4.0 February 1998

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